`timescale 1ns/1ns
module register_test;

    wire [7 : 0] out;
    reg [7 : 0] data;
    reg load, rst_;
    wire clk;

    register r1 (
        .out(out),
        .data(data),
        .load(load),
        .clk(clk),
        .rst_(rst_)
    );

    clock c1 (
        .clk(clk)
    );

    initial begin
        $timeformat(-9, 0, "ns", 5);
        $monitor("time=%t, clk=%b, data=%h, load=%b, out=%h, rst_=%b",
                    $stime, clk, data, load, out, rst_);
        $dumpvars(1, register_test);
    end

    initial begin
        @(negedge clk)
        rst_ = 0;
        data = 0;
        load = 0;
        @(negedge clk)
        rst_ = 1;
        @(negedge clk)
        data = 'H55;
        load = 1;
        @(negedge clk)
        data = 'Haa;
        load = 1;
        @(negedge clk)
        data = 'Hcc;
        load = 0;
        @(negedge clk)
        $finish;
    end
endmodule
